Power - Aware High - Performance Cache Memory

iii Acknowledgements iv Abstract CMOS technology scaling in recent decades has enabled a phenomenal performance improvement in microprocessors by allowing designers to increase the level of integration at higher clock frequencies. Unfortunately, technology scaling has also created unprecedented design challenges, including, but not limited to, the devices' leakage current, the interconnect delay and the clock distribution [5,10,11]. These design challenges, accompanied by a number of architectural innovations, often require serious revisits on the conventional architectural techniques that were acceptable in the past. In this paper, we investigate the impact of CMOS technology scaling on the future high-performance cache designs and observe that leakage energy in high-performance L1 cache designs is tightly coupled with the cache's bitline precharging schemes. Based on the investigation, we expect that conventional bitline precharging schemes will soon be unusable due to their prohibitive leakage energy dissipation, as CMOS technology scales. Therefore, we revisit the high-performance cache's bitline precharging schemes and propose novel schemes which are necessary to resolve the conventional schemes' unprecedentedly large and growing leakage energy waste for a wide spectrum of CMOS technology. High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in significant energy waste in nanoscale CMOS implementations due to high leakage and bitline discharge in the unaccessed subarrays. Recent research advocates bitline isolation to control precharging of individual subar-rays using bitline precharge devices. In this paper, we carefully evaluate the energy and performance trade-offs of bitline isolation, and propose techniques to exploit bitline isolation's potential to eliminate discharge and reduce overall energy in level-one caches. v We propose and evaluate an alternative bitline precharging scheme based on bitline isolation. Bitline isolation is a simple and intuitive technique to reduce leakage energy dissipation in unused bitlines by only precharging in-use bitlines. However, we show that applying bitline isolation is not straightforward. Applying bitline isolation exhibits performance and energy trade-offs depending on CMOS technology, thus it must be done with careful architectural considerations in mind. For past and current CMOS technologies, we propose resizable caches, which reduces about 60% to 70% of the bitline discharge without exposing energy and performance implications of bit-line isolation. Gated precharging, our simple hardware-based bitline precharging mechanism based on the subarray reference locality for future CMOS technologies, captures most of the potential of bitline isolation. The technique removes 93% and 96% of the conventional scheme's energy …